1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection structure and a method of manufacturing such a semiconductor device.
2. Prior Art
Conventional interconnection techniques for semiconductor devices adopt a configuration in which interconnection wiring is arranged in layers laid on top of another with an insulating film provided between the adjacent interconnections layers and in which the wiring formed by an upper interconnection layer is electrically connected to that of an underlying interconnection layer through connection holes formed in the insulating film. This interconnection configuration can significantly affect the characteristics and reliability of the semiconductor device.
Such a multilayer interconnection configuration will be described below with reference to FIGS. 6(a) to 6(d) which show successive stages in a conventional process for manufacturing semiconductor devices.
FIG. 6(a) shows a semiconductor device based on a substrate 71 provided with semiconductor regions 71a, e.g. doped regions, and having an insulating layer 71b formed on its upper surface. A first interconnection layer 72 is composed of wiring formed on the surface of substrate 71 in contact with semiconductor regions 71a. The wiring constituting first interconnection layer 72 is formed by patterning a conductive material deposited on the substrate by sputtering.
To provide a second interconnection layer which provides a second wiring pattern on the semiconductor substrate 71 arranged in the manner described above, an interlayer insulating film 73 is first deposited from above the first interconnection layer 72, as shown in FIG. 6(b), and then connection holes 74 are opened for connecting the first interconnection layer 72 to the second interconnection layer to be formed on the surface of the interlayer insulating film 73, as shown in FIG. 6(c). On the surface of the semiconductor substrate 71 which is in the above-described state, a metal material is deposited by sputtering so as to form a metal layer on the surface of the interlayer insulating film 73 and to fill the connection holes 74. Thereafter, the metal layer is patterned, e.g. by conventional selective etching processes, to form a second interconnection layer 75. Layer 75 provides a wiring pattern composed of connecting paths which are connected to selected paths of first interconnection layer 72 through the connection holes 74 in the interlayer insulating film 73.
In the conventional procedures for manufacturing semiconductor devices, since the connecting holes 74 in the interlayer insulating film 73 are filled from above the semiconductor substrate 71 with metal of the second interconnection layer, the quality of the connection between the paths provided by layers 72 and 75 is more affected by the shape of the lower layer. For example, deposition of the metal material of layer 75 to the lower portion of a connection hole 74 may be impeded or prohibited by the presence of metal material attached to the vicinity of the opening of the top of the connection hole, resulting in the creation of a void in a corner portion 74a at the bottom of the connection hole 74, as shown in FIG. 6(d).
Moreover, since the metal wiring material is not easily deposited on the inner peripheries of connection holes 74, the portion of the second interconnection layer 75 which is located within connection holes 74 may be quite thin.
Such failures associated with coverage by a metal layer providing interconnection wiring lead to an initial connection failure, or open circuit, or a connection failure which appears after a certain period of time due to electromigration or the like. Therefore, it would be desirable to eliminate the causes of such failures.
In order to overcome the aforementioned problems, it has already been proposed to utilize plated interconnection layers as shown in FIG. 7. FIG. 7 shows a semiconductor device in which a conductive subbing layer 83 is deposed on the surface of an interlayer insulating film 82 and on the inner surfaces of connecting holes 82a. In this semiconductor device, a second interconnection layer 84 is deposited and the interiors of the connecting holes 82a are filled with the second interconnection layer 84 by plating which is conducted using the conductive subbing layer 83 as the plating electrode. Therefore, the metal layer can be reliably caused to grow from the surface of the conductive subbing layer 83, and the aforementioned coverage can thus be improved. However, in this method, as the conductive subbing layer 83 is present on the side surface of the connection hole 82a also, if the aspect ratio of the connection hole 82a is high, the metal of second interconnection layer 84 which grows in the vicinity of the top 82b of the connection hole 82a tends to plug the top 82b, thus giving rise to a void 84b in the interior of the connection hole 82a. Consequently, the electric resistance in the interior of the connection hole 82a may be increased, or disconnection may eventually occur due to electromigration. Thus, there are limitations to the range to which plating can be applied to the interconnection structure.
As semiconductor device dimensions, and the lateral length of a single semiconductor device, are reduced, the aspect ratio of the connection holes is increased, thus increasing the likelihood of occurrence the above-described problems.
In view of the aforementioned problems of the conventional technique, an object of the present invention is to provide a semiconductor device in which formation of a connecting portion for electrically connecting interconnection layers to each other is started only from the surface of the interconnection layer located below the connection portion by plating so as to improve the initial characteristics and the reliability.
The above and other objects are achieved, according to the present invention, by the provision of a semiconductor device having a multilayer interconnection structure, comprising: a semiconductor substrate having an upper surface provided with a patterned interconnection area containing semiconductor element regions; a conductive first subbing layer deposited on the patterned interconnection area; a first interconnection layer composed of first interconnection layer portions deposited on the conductive subbing layer and electrically connected to the semiconductor element regions through the conductive subbing layer; a metal connection layer composed of connection layer portions formed on the first interconnection layer portions by plating; an interlayer insulating film deposited on the first interconnection layer portions around the metal connection layer portions for burying the metal connection layer portions in such a manner that the tops of the metal connection layer portions are exposed; and a second interconnection layer composed of second interconnection layer portions deposited on the interlayer insulating film and electrically connected to the first interconnection layer portions through the metal connection layer portions.
The objects of the invention are further achieved by the practice of a method of manufacturing a semiconductor device having a multilayer structure, comprising: providing a semiconductor substrate having an upper surface provided with a patterned interconnection area containing semiconductor element regions; depositing a conductive subbing layer on the upper surface of the semiconductor substrate; depositing a first interconnection layer composed of first interconnection layer portions on the conductive subbing layer; covering the first interconnection layer with a mask having windows corresponding to portions of a metal connection layer; forming, in the mask windows, a metal connection layer composed of connection layer portions on portions of the first interconnection layer; removing the mask from the first interconnection layer; removing portions of the conductive subbing layer from locations surrounding the portions of the first interconnection layer; forming an interlayer insulating film on the first interconnection layer portions around the metal connection layer portions for burying the metal connection layer portions in such a manner that the tops of the metal connection layer portions are exposed; and depositing a second interconnection layer composed of second interconnection layer portions on the interlayer insulating film.
In a case where the first interconnection layer is formed on the surface of the conductive subbing layer by plating, the first interconnection forming step includes a step of covering the surface of the conductive subbing layer with a mask having a window portion corresponding to a patterned interconnection area of the first interconnection layer to be formed, and a step of forming by plating the first interconnection layer on the portion of the surface of the conductive subbing layer which is located in the window portion. This mask is removed in the mask removing step. In that case, it is desired to form the first interconnection layer in such a manner that the side surfaces of the first interconnection layer portions are tapered so as to make the tops thereof are narrower than the bottoms, thereby allowing the interlayer insulating film to be deposited more reliably close to the side surfaces of the first interconnection layer portions.
This is achieved by the use of a mask made of a negative type photoresist during the first interconnection layer forming process.
The insulating film forming procedure includes the step of depositing the insulating film from above the first interconnection layer in such a manner that the upper portion of the metal connection layer is covered with the insulating film, and the step of conducting etch back until at least the surface of the metal connection layer is exposed. In that case, it is desired that the etch back be conducted until the upper portion of the metal connection layer protrudes from the surface of the interlayer insulating film so as to increase the contact area between the metal connection layer and the second interconnection layer.
The subbing layer removing step includes dry etching which is conducted using the first interconnection layer as a mask. It is desired to make the periphery of the upper surface of the metal connection layer and the periphery of the upper surface of the first interconnection layer a curved surface so that the interlayer insulating film is deposited close to the first interconnection layer. This is achieved by conducting dry etching until the upper surface of the metal connection layer and the upper surface of the first interconnection layer are removed.
The first interconnection layer, the metal connection layer and the second interconnection layer are made of a metal selected from the group consisting of Au, Ag and Cu.
It is also desired to construct the conductive subbing layer so that it is composed of a lower layer made of a metal which is either Ti or Mo and an upper layer made of a metal which is either the same metal as the second interconnection layer or Pt.
In the present invention, after the conductive subbing layer is deposited on the surface side of the semiconductor substrate in the subbing layer forming step, the first interconnection layer is formed by plating on the surface of the conductive subbing layer. At this time, the conductive subbing layer is left unremoved. After the surface of the first interconnection layer is covered with a mask having windows corresponding to the portions constituting the metal connection layer, the semiconductor substrate is plated using the conductive subbing layer as an electrode so as to form the metal connection layer in the windows. Thereafter, the conductive subbing layer is removed from the substrate surface regions which are not covered by portions of the first interconnection layer. In that state, the metal connection layer is buried in the interlayer insulating film in such a manner that the tops of the metal connection layer portions are exposed.
Subsequently, the second interconnection layer is formed by repeating the above processes or by sputtering. In this way, the second interconnection layer is electrically connected to the metal connection layer which is exposed through the interlayer insulating film, which is in turn electrically connected to the first interconnection layer. As the metal connection layer is formed by plating on the surface of the first interconnection layer before the interlayer insulating film is formed, it is not necessary to fill the connection holes in the interlayer insulating film, as in the conventional case. Hence, the metal connection layer adheres well to the first interconnection layer, and no void is generated in the metal connection layer even when the metal connection layer is thick. It is therefore possible to provide an interconnection structure which has a low interconnection resistance and which is capable of preventing generation of electromigration and thereby improves the initial characteristics and reliability of the semiconductor device.